Instruction Set Matrix

Each instruction word is 32-bits in length.

The instruction to execute is based on bits 26-31:

SPECIAL REGIMM J JAL BEQ BNE BLEZ BGTZ
ADDI ADDIU SLTI SLTIU ANDI ORI XORI LUI
COP0 COP1 COP2 COP3 INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
LB LH LWL LW LBU LHU LWR INVALID
SB SH SWL SW INVALID INVALID SWR INVALID
LWC0 LWC1 LWC2 LWC3 INVALID INVALID INVALID INVALID
SWC0 SWC1 SWC2 SWC3 INVALID INVALID INVALID INVALID

Note that COP1, COP3, LWC0, LWC1, LWC3, SWC0, SWC1, SWC3 have special handling even though they are not technically defined on the PS1.

The SPECIAL subinstruction to execute is based on bits 0-5:

SLL INVALID SRL SRA SLLV INVALID SRLV SRAV
JR JALR INVALID INVALID SYSCALL BREAK INVALID INVALID
MFHI MTHI MFLO MTLO INVALID INVALID INVALID INVALID
MULT MULTU DIV DIVU INVALID INVALID INVALID INVALID
ADD ADDU SUB SUBU AND OR XOR NOR
INVALID INVALID SLT SLTU INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID

The REGIMM subinstruction to execute is based on bits 16-20:

BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ
BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ
BLTZAL BGEZAL BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ
BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ BLTZ BGEZ

As can be seen here, 0x02-0x0f and 0x12-0x1f are mirrors of 0x00-0x01 (BLTZ and BGEZ)

The COP0 (SCC) subinstruction to execute is based on bits 21-25:

MFC0 INVALID INVALID INVALID MTC0 INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
COP0X COP0X COP0X COP0X COP0X COP0X COP0X COP0X
COP0X COP0X COP0X COP0X COP0X COP0X COP0X COP0X

When bit 25 is set, the COP0 subinstruction is further specialized.

The COP0X sub-subinstruction to execute is based on bits 0-5:

INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
RFE INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID

The COP2 subinstruction to execute is based on bits 21-25:

MFC2 INVALID CFC2 INVALID MTC2 INVALID CTC2 INVALID
INVALID INVALID INVALID INVALID INVALID INVALID INVALID INVALID
COP2X COP2X COP2X COP2X COP2X COP2X COP2X COP2X
COP2X COP2X COP2X COP2X COP2X COP2X COP2X COP2X

When bit 25 is set, the COP2 subinstruction is further specialized.

The COP2X sub-subinstruction to execute is based on bits 0-5:

RTPS RTPS INVALID INVALID INVALID INVALID NCLIP INVALID
INVALID INVALID INVALID INVALID OP INVALID INVALID INVALID
DPCS INTPL MVMVA NCDS CDP INVALID NCDT INVALID
INVALID INVALID DCPL NCCS CC INVALID NCS INVALID
NCT INVALID INVALID INVALID INVALID INVALID INVALID INVALID
SQR DCPL DPCT INVALID INVALID AVSZ3 AVSZ4 INVALID
RTPT INVALID INVALID INVALID INVALID INVALID INVALID INVALID
INVALID INVALID INVALID INVALID INVALID GPF GPL NCCT

RTPS 0x01 is a mirror of 0x00. DCPL 0x29 is a mirror of 0x1a.